Field of the invention
The invention lies in the memory technology field and relates, specifically, to a RAM memory circuit, in particular a dynamic RAM memory circuit (DRAM). The circuit has at least one memory bank, which comprises a multiplicity of memory cells arranged in matrix organization in rows and columns and is subdivided into a plurality of areas which can be cyclically connected to a common data port by way of an area multiplexer.
The RAM memory circuit of the generic type may be described as follows:
At least one memory bank is divided into q≧2 areas and includes a multiplicity of memory cells in a matrix in rows and columns, the set of the columns of each area being subdivided into p≧2 disjoint subsets, each of which defines a segment;
For each area there is provided a dedicated area bus and for each segment of each area there is provided a bundle of m≧1 master data lines which branches from the relevant area bus and, for its part, can be connected via a line network, which can be controlled by address information, to individually addressed groups of in each case m memory cells within a respective segment.
An area multiplexer is enabled to cyclically connect the area buses to a data port, which has m external terminals for inputting and outputting the data groups that are to be written in or read out at the addressed memory cell groups.
Delay or holding means simultaneously provide in each case q successive data groups on the q area buses.
A control device controls the write and read operation under the influence of an applied clock signal and applied address information and command information.
Memory circuits of this generic type allow data streams that are to be written in and read out to be input and output, respectively, via the data port at a data rate which corresponds to a multiple of the internal write clock and read clock at the memory bank. The invention also relates to a method for operating a memory circuit of this type.
The data streams which are input and output at RAM memory circuits may have a width of one or more bits. Thus, in general terms, the data stream is a sequence of “data groups”, each of which comprises m≧1 parallel bits which are input and output via an m-bit parallel port. The term data rate denotes the repetition frequency of the data groups during inputting and outputting. The data are usually handled in so-called data “bursts”, i.e. a plurality of directly successive data groups are input or output during each write or read operation. The number of data groups per burst, the so-called “burst length”, can be set as a setting parameter at the control device of the memory circuit.
Each data group allocates a group of m memory cells which can be addressed by selection of a row, which is done by activating a row select line (word line) assigned to the row in a manner dependent on a row address (X address), and by selection of a group of m columns in a manner dependent on a column address (Y address). As a result of this row and column addressing, in a controllable data path network covering the memory bank, a data path is switched through which connects the addressed memory cell group to an internal m-bit data bus in order to write an m-bit data group to the addressed memory cell group via the bus, or to read it from the group.
The universal set of the columns of the memory bank is thus organizationally subdivided into disjoint groups of in each case m columns. Larger memory banks are additionally subdivided into a plurality of so-called “segments”, each of which comprises an identical number of column groups. Usually, the universal set of the rows is also subdivided into disjoint, equipotent groups. The set of memory cells which belong to the same row group within a segment is referred to as a “domain”.
The data path network is constructed hierarchically in accordance with these subdivisions: each domain contains a column line, referred to as “bit line,” along each column and there is situated at each memory cell a cell selection switch for optionally connecting the cell to the bit line of the relevant column. For its part, each group of m bit lines belonging to a column group of the domain can be connected selectively via m assigned group selection switches to a bundle of m local data lines which is assigned to the entire domain. For its part, each of these bundles can be connected selectively via m assigned domain selection switches to a bundle of m master data lines which is assigned to the entire segment. Each of these bundles can be connected selectively to the internal m-bit data bus.
With the activation of a word line, selected by the row address, the cell selection switches are closed at all the memory cells of the relevant row. The row address and the column address determine the domain in order to ascertain which domain selection switch is to be closed. In addition, the column address determines which group selection switches within the domain are to be closed and which master data line bundle is to be connected to the internal data bus in order to switch through the data path between the bus and the addressed memory cell group.
The technique of operation at a multiplied data rate as mentioned in the introduction has been customary to a great extent for some time. For instance, published U.S. patent application Ser. No. 2001/0033522 A1, describes a circuit for “double data rate” (DDR) operation. There, the bank is additionally subdivided into two disjoint “areas”, each of which comprises one half of the universal set of the columns, to be precise in such a way that each area comprises the same number of whole segments. Each area is assigned a dedicated m-bit data bus as a so-called “area bus”. The stream of the data groups to be written in or read out, which are input or output, respectively, as a sequence successively via the data port, is split into two partial streams internally by means of the area multiplexer, in such a way that the successive data groups are alternately assigned to different areas. The two areas are operated synchronously with the same clock timing, so that two data groups are in each case written or read simultaneously (that is to say at the same time), while the inputting and outputting of the sequence of data groups via the data port takes place sequentially (that is to say one after the other with respect to time) at double the frequency of the clock, with correspondingly rapid actuation of the area multiplexer. In order to enable the transition between simultaneous and sequential, either a delay by one period of the data rate (half a period of the access clock) has to be inserted at one of the area buses, or a holding circuit (bus data latch) has to be connected to at least one of the area buses.
In order to realize RAM memories which are to be operated at an even higher data rate, the (for each) memory bank is to be subdivided into correspondingly more disjoint areas, each with the same number of whole segments and with a dedicated area bus. In general terms: for a q-fold data rate (where q≧2), it is necessary to define q areas and to provide q area buses, and the area multiplexer is to be designed for cyclically changing over the data port between the q area buses. Consequently, in the case of each “access clock” (write or read clock at the bank), q data groups can be written or read at the q areas, the inputting and outputting of the data groups via the data port taking place one after the other with respect to time at a data rate corresponding to q times the frequency of the clock, with correspondingly rapid actuation of the area multiplexer. Hereinafter, a RAM memory circuit of this general generic type shall be designated as qDR-RAM for short.
In order to write data to a RAM bank, in the case of the prior art, an external write command is applied to the memory circuit. In the case of a qDR-RAM, before the beginning of the actual write operation at the bank for switching through the data paths to the respectively addressed memory cell groups after validity of the write command, it is necessary to wait until the first q data groups which can be simultaneously written to the q areas are present in valid fashion on the q area buses. This write start-up time comprises a command evaluation time (setup time), furthermore the bus latency (propagation time of the data from the data port via the multiplexer and the length of the data buses) plus q−1 periods of the data rate. Thus, the sequence of the column select signals which are applied to the switches in the data path network at the frequency of the access clock for switching through the data paths is permitted to be started only after the the start-up time has elapsed. The write operation is ended when the last data group has reached the memory cell group allocated to it, that is to say with the end of the last column select signal. In conventional RAMs, all the area buses are occupied with write data up to this point in time.
In order to read data at the bank, in the case of the prior art, an external read command is applied to the memory circuit, and the sequence of column select signals is begun with the access clock after the command evaluation time has elapsed. Once the first read data group is available at the master data line bundle of the relevant segment with the ending of the first column select signal, the above-mentioned bus latency also elapses before the data group has reached the data port in valid fashion. The total duration from the read command up to this point in time is generally referred to as “CAS latency”.
It happens during practical use of RAM memory circuits that it is necessary to change between write and read operation within the same row of memory cells. In the case of qDR-RAMs according to the prior art, each area bus is permanently coupled to all the master data line bundles of the relevant area, usually via bidirectional amplifier circuits, the so-called “secondary amplifiers”. Since, as mentioned above, all the area buses are occupied until the end of the last column select signal of a write operation, a subsequent read access cannot be begun until after this point in time. The consequence of this is that the first column select signal of the read access can only be applied at the earliest after one full period of the access clock (q periods of the data rate).